Generally, a redundancy device is a defect repair device that replaces a bit line connected to a possible defective cell of a cell array with a spare bit line. When an address corresponding to the defective cell is applied to a memory device, a normal path for selecting the defective cell is disconnected and the redundancy device operates to enable a bit line connected to a repaired cell so as to perform a redundancy operation.
The redundancy scheme is classified into either a row redundancy type or a column redundancy type according to the type of a spare memory cell used to replace a defective cell. The row redundancy technique replaces a defective cell with a spare row (or a redundant word line), and the column redundancy technique replaces a defective cell with a spare column (or a redundant bit line). The row redundancy technique is further classified as a folded bit line type or an open bit line type. In the folded bit line row redundancy technique, a bit line and a bit line bar, which are formed in one memory cell block, are connected to one sense amplifier. In the open bit line row redundancy technique, a bit line and a bit line bar, which are formed in different memory cell blocks, are connected to one sense amplifier.
FIG. 1 is a conceptual diagram illustrating a data output operation of a conventional memory device having a folded bit line sense amplifier. In FIG. 1, it is assumed that each bit line is connected to one sense amplifier (S/A). When a word line W/L corresponding to a row address is selected and a bit line corresponding to a column address is enabled, each S/A senses data through the enabled bit line and outputs the sensed data via a plurality of data pins DQ=0, 1, 2, 3, 4, 5, 6, 7. One cell array block (or memory bank) having a block A1 and a block B1 is illustrated in FIG. 1, and each of the blocks A1 and B1 includes 8K (K represents a number of 1,024) word lines W/Ls. A word line W/L whose row address is one of 0–8K is illustrated in FIG. 1.
Because one word line W/L is enabled within a refresh range of 8K in a normal W/L enable operation, two word lines W/L1 and W/L2 are enabled in one cell array block. Word lines W/Ls are enabled in all row blocks in the same way as above. Also, a row redundancy enable operation is processed in the same manner as the normal W/L enable operation.
When a row redundancy repair technique is applied to the conventional folded bit line sense amplifier, a defective W/L is replaced with a spare W/L on a 1:1 basis. For example, a spare W/L corresponding to a defective W/L is enabled in a refresh range of 8K in the same way as above, and thus two W/Ls are enabled.
However, in a memory device having an open bit line S/A architecture, a dummy bit line 20 exists at the last edge block of a memory bank. A dummy bit line processing method is generally classified into either a round edge block processing method or a straight edge block processing method. FIGS. 2 and 3 schematically depict a straight edge block processing method for processing a dummy bit line. In particular, FIG. 2 is a conceptual diagram illustrating a case where two word lines are enabled and thus eight DQ data are outputted by a memory device having a conventional open bit line sense amplifier, and FIG. 3 is a conceptual diagram illustrating a case where three word lines are enabled and thus eight DQ data are outputted by a memory device having a conventional open bit line sense amplifier. FIGS. 2 and 3 illustrate one cell array block having blocks A2 and B2, wherein each block A2 and B2 includes 8K word lines W/Ls.
Referring to FIG. 2, the block A2 includes a first edge sub-block 10 (that is, a left edge block) corresponding to row addresses X of 0–255 and a first main sub-block 20 corresponding to row addresses X of 256–8K. The block B2 includes a second edge sub-block 30 (that is, a center pseudo edge block) corresponding to row addresses X of 0–255, a second main sub-block 40 corresponding to row addresses X of 256–8K, and a dummy sub-block 50 corresponding to row addresses X of 0–255.
As illustrated in FIG. 2, when the W/Ls of the main blocks 20 and 40 are enabled in the open bit line S/A architecture, two W/Ls 12 and 22 are enabled in the same way as the folded bit line S/A architecture and thus a total of eight DQ data are outputted. In addition, in a row redundancy operation, two W/Ls of redundancy cells selected from the main blocks 20 and 40 are enabled in the same way as the conventional folded bit line technique.
However, when DQ data needs to be output using the first edge sub-blocks 10, the second edge sub-block 30 and the dummy sub-block 50, as shown in FIG. 3, three W/Ls 11, 13 and 21 (not two W/Ls) must be enabled. Therefore, the case where DQ data are outputted using the sub-blocks is different from a case where DQ data are outputted using the main blocks. Also, when row defects occur at the first edge sub-block 10, the second edge sub-block 30 and the dummy sub-block 50, a corresponding row redundancy repair operation must be processed differently from the normal operation.
Moreover, in case the dummy bit line of the memory device having the conventional open bit line architecture is processed through the straight edge block processing method, repair efficiency is degraded when a repair process is performed in a self-block.